1. Field of the Disclosure
The present disclosure generally relates to synchronous circuits and, more particularly, to a method and apparatus for initializing a delay locked loop (DLL).
2. Brief Description of Related Art
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
In SDRAMs or other semiconductor memory devices, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. Delay locked loops (DLLs) are synchronous circuits used in SDRAMs to synchronize an external clock (e.g., the system clock serving a microprocessor) and an internal clock (e.g., the clock used internally within the SDRAM to perform data read/write operations on various memory cells) with each other. Typically, a DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal (e.g., the system clock) is advanced or delayed until its rising edge is coincident (or “locked”) with the rising edge of a second clock signal (e.g., the memory internal clock). A brief discussion of the operation of a DLL is provided hereinbelow with reference to FIG. 1.
Turning to FIG. 1, the delay of the forward delay path of a delay locked loop 10 is given by the equation:d1+[N*tCK−(d1′+d2′]+d2=N*tCK 
In FIG. 1, the clock-to-strobe time [(B)-to-(A)] is equal to N*tCK. If the time from node (B) to (A) is N*tCK, then the portion in the delay line is: N*tCK−(d1′+d2′). That allows the DLL 10 to be initialized through inputting a measurement into the “broadside” of the shift register, i.e. a broadside measurement.
The current method of initializing the DLL 10 with a delay measurement (measure initialization) bypasses the DLL's forward delay line 12 through the operation of a multiplexer (MUX) 14 during DLL initialization. That ensures that the measurement is independent of the forward delay line 12 delay. However, anytime the forward delay line is bypassed, the clock propagating to the outputs may not be synchronized to the external clock.
During measurement time, the output clock timing is unknown (or at least, will not provide clock synchronization). Before causing the measurement strobe to fire, enough time must be allowed to ensure that the new, bypassed clock propagates fully through the I/O model 20 (d1′+d2′) and into the measure delay line 18. That may take several clock cycles. As a result, the outputs cannot be synchronized anytime that a measurement is performed. If a new measurement is necessary, the outputs must not be used for several clock cycles.
Thus, a need exists for a DLL and method of operating a DLL that enables the old clock timing to continue to control the delay line until the new measurement is ready to control the delay line.